Verilog HDL Notes-Basic Introduction
Verilog HDL Notes-Basic Introduction
4 Basic Models of Verilog
RTL V.S. Behavioral
- RTL: it specifies how data flows between registers and logic gates. Allowing you to optimize the circuit by controlling the number and type of registers and logic gates. (MORE SUITABLE FOR SYNTHESIS)
- Behavioral: it describes the behavior of the circuit at a higher level of abstraction, without specifying the details of the hardware implementation. Allowing you to model complex or abstract features of the circuit, without worrying about the hardware implementation. (MORE SUITABLE FOR SIMULATION)
Data Types
Basic Operations
Basic Blocks
for loop v.s. generate for loop
- For loop: a regular for loop in Verilog is a procedural statement used to iterate over a block of code during simulation. It is typically used inside procedural blocks such as always, initial, or within tasks and functions.
- Generate for loop: The generate block combined with a for loop allows you to instantiate multiple hardware components (e.g., modules, registers, gates) based on a loop index.
task and function
- Referencel: verilog中的任务task和函数function用法及区别
Ways of Assignments
Blocking assignment v.s. Non-blocking assignment
- Blocking Assignment: A blocking assignment in Verilog uses the " = " operator. It executes sequentially, just like traditional programming languages such as C or Python.
- A non-blocking assignment in Verilog uses the " <= " operator. It executes parallelly, and the actual assignment is deferred until the end of the simulation time step.
Port-Net Mapping
Port-Associated Mapping v.s. Ordered Mapping
- Port-Associated: M1 U1(.A(Node2), .CLK(Wire1), .B(Net3))
- Ordered Mapping: M1 U1(Wire1, Node2, Net3)
- Title: Verilog HDL Notes-Basic Introduction
- Author: Shih Jiun Lin
- Created at : 2024-10-12 07:20:00
- Updated at : 2024-10-12 20:04:34
- Link: https://shih-jiun-lin.github.io/2024/10/12/Verilog HDL Notes-Basic Introduction/
- License: This work is licensed under CC BY-NC-SA 4.0.