Mod_N Counter-數位邏輯技術

Shih Jiun Lin Lv4

Mod_N Counter-數位邏輯技術

Introduction to Counter

Main Idea of the Implementation of Mod_N Counter

Main Idea of the Implementation

  • A Mod-N counter is triggered by a clock. After declaring a variable (countr) to store counting information, when rising edge of a clock is detected, . When , clear countr to zero.

  • In order to observe the changing of numbers, the code below uses a frequency divider.(1hz)

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is
port (
CLK : in std_logic;
COUNT : out std_logic_vector(3 downto 0)
);
end entity counter;

architecture behavioral of counter is

component to_1hz_divider is
port(

CLK_IN: in std_logic;
CLK_OUT: out std_logic

);
end component;

signal CLK_COUNTR: std_logic;
signal countr: std_logic_vector(4 downto 0);

begin

divider: to_1hz_divider
port map(

CLK_IN => CLK,

CLK_OUT => CLK_COUNTR

);

process(CLK_COUNTR)
begin

if rising_edge(CLK_COUNTR) then

countr <= countr + 1;

end if;

if countr(4) = '1' then

countr <= (others => '0');

end if;

end process;

COUNT <= countr(3 downto 0);

end architecture behavioral;
  • With 7-seg display
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    library ieee;
    use ieee.std_logic_1164.all;

    entity counter_with7seg is
    port(

    CLK_50mhz: in std_logic;

    display: out std_logic_vector(6 downto 0)

    );
    end entity;

    architecture behavioral of counter_with7seg is

    signal data_temp: std_logic_vector(3 downto 0);

    component counter is
    port (
    CLK : in std_logic;
    COUNT : out std_logic_vector(3 downto 0)
    );
    end component;

    component seven_segement_decoder is
    port (
    data: in std_logic_vector(3 downto 0);
    display: out std_logic_vector(6 downto 0)
    );
    end component;

    begin

    countr: counter
    port map(

    CLK => CLK_50mhz,

    count => data_temp
    );

    display0: seven_segement_decoder
    port map(

    data => data_temp,

    display => display
    );

    end behavioral;
  • Title: Mod_N Counter-數位邏輯技術
  • Author: Shih Jiun Lin
  • Created at : 2023-11-12 23:00:00
  • Updated at : 2023-11-12 23:35:25
  • Link: https://shih-jiun-lin.github.io/2023/11/12/Mod_N Counter/
  • License: This work is licensed under CC BY-NC-SA 4.0.