The Design of Multiplier-數位邏輯技術

Introduction to Multiplier

Implementation of 4-bit multiplier with CLA

Main Idea of the Implementation

• 

• 

VHDL implementation

library ieee;
use ieee.std_logic_1164.all;

entity multiplier is
	port(
		a: in std_logic_vector(3 downto 0);
		b: in std_logic_vector(3 downto 0);
		result: out std_logic_vector(7 downto 0)
	);
end multiplier;

architecture behavioral of multiplier is

component adder4multiplier is
	port(
		x: in std_logic_vector(3 downto 0);
      y: in std_logic_vector(3 downto 0);
      sel: in std_logic; --signal to do addition or subtraction
      s: out std_logic_vector(3 downto 0);
      co: out std_logic --carry from last bit
	);	
end component;

component adder4multiplier is
	port(
		bin :in std_logic_vector (7 downto 0);
		bcd0 : out std_logic_vector (3 downto 0);
		bcd1 : out std_logic_vector (3 downto 0);
		bcd2 : out std_logic_vector (3 downto 0)
	);
end component;

signal anb0, anb1, anb2, anb3: std_logic_vector(3 downto 0);
signal y_4_adder0, y_4_adder1, y_4_adder2: std_logic_vector(3 downto 0);
signal sum0, sum1, sum2: std_logic_vector(3 downto 0);
signal carry0, carry1, carry2: std_logic;

---a and with each bit in b
begin
	a_and_b: process(a, b)
		begin
			for i in 0 to 3 loop
				anb0(i) <= b(0) and a(i);
				anb1(i) <= b(1) and a(i);
				anb2(i) <= b(2) and a(i);
				anb3(i) <= b(3) and a(i);
		end loop;
	end process;
	---

	--- data for y in adder_0
	data_4_adder0: process(anb0)
		begin
			for i in 0 to 2 loop
				y_4_adder0(i) <= anb0(i+1);
		end loop;
	end process;
		
	y_4_adder0(3) <= '0';	
	---

	adder_0: adder4multiplier
			port map(
				x => anb1,
				y => y_4_adder0,
				sel => '0',
				s => sum0,
				co => carry0
			);

	--- data for y in adder_1
	data_4_adder1: process(sum0)
		begin
			for i in 0 to 2 loop
				y_4_adder1(i) <= sum0(i+1);
		end loop;
	end process;

	y_4_adder1(3) <= carry0;	
	---		

	adder_1: adder4multiplier
			port map(
				x => anb2,
				y => y_4_adder1,
				sel => '0',
				s => sum1,
				co => carry1
			);
			
	--- data for y in adder_2
	data_4_adder2: process(sum1)
		begin
			for i in 0 to 2 loop
				y_4_adder2(i) <= sum1(i+1);
		end loop;
	end process;

	y_4_adder2(3) <= carry1;	
	---		

	adder_2: adder4multiplier
			port map(
				x => anb3,
				y => y_4_adder2,
				sel => '0',
				s => sum2,
				co => carry2
			);

	---processing result
	result(0) <= anb0(0);
	result(1) <= sum0(0);
	result(2) <= sum1(0);

	z3_to_z6: process(sum2)
		begin
			for i in 0 to 3 loop
				result(i+3) <= sum2(i);
		end loop;
	end process;

	result(7) <= carry2;
	---

end behavioral;

Implementation of 8-bit multiplier based on 4-bit multiplier with data shifting

Main Idea of the Implementation

• Basically, the idea is dividing both data into two part and do 4-bit multiplication. After the multiplication, we shift all the result and do addition. (反正就直式乘法的概念)

• Take for example => (a, b, c, d are all 4-bit data)

VHDL implementation

library ieee;                       
use ieee.std_logic_1164.ALL; 
use ieee.numeric_std.all;  
use ieee.std_logic_unsigned.all;

entity multiplier_8bits is
	port(
		x: in std_logic_vector(7 downto 0);
		y: in std_logic_vector(7 downto 0);
		output: out std_logic_vector(15 downto 0)
	);
end multiplier_8bits;

architecture behavioral of multiplier_8bits is

component multiplier is
	port(
		a: in std_logic_vector(3 downto 0);
		b: in std_logic_vector(3 downto 0);
		result: out std_logic_vector(7 downto 0)
	);
end component;
	
signal temp0, temp1, temp2, temp3: std_logic_vector(3 downto 0);
signal result0, result1, result2, result3: std_logic_vector(7 downto 0);
signal add0, add1, add2, add3: std_logic_vector(15 downto 0);
signal result_readable: std_logic_vector(15 downto 0);
	
begin 

	---processing temp0123
	temp0 <= x(7 downto 4);
	temp1 <= x(3 downto 0);
	temp2 <= y(7 downto 4);
	temp3 <= y(3 downto 0);

	---processing 4 bits multipplication 
	multiplier0: multiplier
		port map(
			a => temp1,
			b => temp3,
			result => result0
		);

	multiplier1: multiplier
		port map(
			a => temp0,
			b => temp3,
			result => result1
		);

	multiplier2: multiplier
		port map(
			a => temp2,
			b => temp1,
			result => result2
		);

	multiplier3: multiplier
		port map(
			a => temp0,
			b => temp2,
			result => result3
		);

	---doing shift on the result of 4 bits multiplication
	add0(7 downto 0) <= result0;
	add1(11 downto 4) <= result1;
	add2(11 downto 4) <= result2;
	add3(15 downto 8) <= result3;

	---doing addition
	result_readable <= std_logic_vector(unsigned(add0) + unsigned(add1) + unsigned(add2) + unsigned(add3));  
	output <= result_readable;

end behavioral;