The Design of Frequency Divider-數位邏輯技術

Frequency Divider-數位邏輯技術

Introduction to Frequency Divider

• When a high frequency signal source is provided, you can lowering the frequency of the signal by applying frequency divider.

Implementation of Frequency Divider

Main Idea of the Implementation

• Take a 50Mhz signal for example
  • 50Mhz source will provide 50M high signal in 1 second. To lowering it down to 1hz, we can simply do it by reading the input. If 50M high signal is being read, then output ONE high signal. By doing so, the frequency will be lowered to 1 hz.

50Mhz to 1hz Frequecny Divider VHDL Implemnetation

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity to_1hz_divider is
	port(
		
		CLK_IN: in std_logic;
		CLK_OUT: out std_logic
	
	);
end to_1hz_divider;

architecture behavioral of to_1hz_divider is

signal count: integer := 0;

begin 
	
	process(CLK_IN)
	begin 
		
		if rising_edge(CLK_IN) then
		
			count <= count + 1;
		
			if count = 50000000 then
			
				CLK_OUT <= '1';
				
				count <= 0;
			
			else 
				
				CLK_OUT <= '0';
			
			end if;
		
		end if;
	
	end process;

end behavioral;

CODE LINK