The Design of Carry-lookahead Adder and Subtractor-數位邏輯技術

The Design of Carry-lookahead Adder and Subtractor

Introduction to Carry-lookahead Adder and Subtractor

References

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Simple Explanation

• Basically, the main idea of carry-lookahead adder is doing the calculation of carry before doing the addition.
  • To do so, we have to generate both (propagate) terms and (Generate) terms.
  • After the calculation of all carrys, we have to do the summation/addition.
  • The final step is to proccess the result.
    • To check if overflow occurs:
    • The sign of the result: the last bit of the result equals to its sign.
    • The value of carry_out: the last bit of carry is the value of carry_out.

The VHDL code of Carry-lookahead Adder

Carry-lookahead Adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity carry_lookahead_adder is
	Port( 
	    x: in std_logic_vector(3 downto 0);
        y: in std_logic_vector(3 downto 0);
        sel: in std_logic; --signal to do addition or subtraction
        co: out std_logic; --carry from last bit
		overflow: out std_logic; --to check if overflow occurs
		sign: out std_logic --to display the sign of the result
	);
end carry_lookahead_adder;

architecture behavioral of carry_lookahead_adder is

signal sum_temp, sum, y_final: std_logic_vector(3 downto 0) := "0000";
signal c : std_logic_vector(4 downto 0) := "00000"; --c4 for last carry(cout)
signal p : std_logic_vector(3 downto 0) := "0000"; 
signal g : std_logic_vector(3 downto 0) := "0000"; 

begin
	y_to_2s: process(y) --to do 2's complement if sel is 1
		begin
			if(sel='1') then
				y_final <= not(y) + sel; 
			else
				y_final <= y;
			end if;
	end process;
	
	sum_temp <= x xor y_final; 
   
	g <= x and y_final; --to generate term g
    p <= x or y_final; --to generte term p
	
	c(0) <= '0'; --assign 0 to c(0)
	
    cla: process(c, p, g)
	    begin
		    clc: for i in 0 to 3 loop --carry lookahead circuits
				c(i+1) <= g(i) or (p(i) and c(i)); 
		end loop;
	end process;
	 
    co <= c(4); 
    sum <= sum_temp xor c(3 downto 0); 
	s <= sum;
	overflow <= c(4) xor c(3);
	sign <= sum(3);
end behavioral;

Carry-looahead Adder with two sign control and application of 7-seg Decoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity carry_lookahead_adder is
	Port( 
		x: in std_logic_vector(3 downto 0);
        y: in std_logic_vector(3 downto 0);
        sel_x: in std_logic;
		sel_y: in std_logic;
        s: out std_logic_vector(3 downto 0);
        co: out std_logic;
		overflow: out std_logic;
		sign: out std_logic;
		sgd: out std_logic_vector(6 downto 0) --for resulut display with 7seg display
	);
end carry_lookahead_adder;

architecture behavioral of carry_lookahead_adder is

signal sum_temp, sum, y_final, x_final,  sum_display: std_logic_vector(3 downto 0) := "0000";
signal c : std_logic_vector(4 downto 0) := "00000"; --c4 for last carry(cout)
signal p : std_logic_vector(3 downto 0) := "0000"; 
signal g : std_logic_vector(3 downto 0) := "0000"; 

component seven_segement_decoder is
	port(
		data: in std_logic_vector(3 downto 0);
		display: out std_logic_vector(6 downto 0)
	);	
end component;

begin
	x_to_2s: process(x) --2's complement of data x
		begin
			if(sel_x='1') then
				x_final <= not(x) + sel_x;
			else
				x_final <= x;
			end if;
	end process; --2's complement of data y
	
	y_to_2s: process(y)
		begin
			if(sel_y='1') then
				y_final <= not(y) + sel_y;
			else
				y_final <= y;
			end if;
	end process;
	
	sum_temp <= x_final xor y_final; 
    g <= x_final and y_final; 
    p <= x_final or y_final; 
	c(0) <= '0';
	
    cla: process(c, p, g)
		begin
			clc: for i in 0 to 3 loop --carry lookahead circuits
				c(i+1) <= g(i) or (p(i) and c(i)); 
		end loop;
	end process;
	 
    co <= c(4); 
    sum <= sum_temp xor c(3 downto 0);
	sum_display <= sum;
	overflow <= c(4) xor c(3);
	sign <= sum(3);
	
	sgd_num: seven_segement_decoder
		port map(
			data => sum_display,
			display => sgd
		);
end behavioral;

Source Code

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