Combinational Circuit Design/Simulation Using Gates-數位邏輯設計筆記

一定愛配王俊堯教授開放課程食用:課程連結

Combinational Circuit Design and Simulation Using Gates

Circuit with Limited Gate Fan-In

• Ex1

  

• Ex2

  

Gate Delay and Timing Diagrams

• In real life, there are delays between logic gates.

• There are also delays happening inside logic gates, since it needs time to process the signals.

• Controlling Value vs Noncontrolling Value

  • Controlling Value
    • AND/NAND: 0.
    • OR/NOR: 1.
  • Noncontrolling Value
    • AND/NAND: 1.
    • OR/NOR: 0.

• Ex:

  • Ex1

  

  • Ex2

  

  • Ex3

  

  • Ex4

  

Hazard in Combinational Logic

What is hazard(危障)?

• Unwanted switching transients happening while the input of a combinational circuit suddenly changes.
• It is also called "glitch".

Types of Hazard

• Static 1-hazard
  • Input change causes output to go from 1 to 0.
• Static 0-hazard
  • Input change causes output to go from 0 to 1.
• Dynamic hazards
  • To go from 0 to 1, a glitch happens during the process.
  • To go from 1 to 0, a glitch happens during the process.

When will hazzard happen?

Examples

• Ex1(Static 1-hazard):

  • When input chages from (A,B,C)=(1,1,1) to (A,B,C)=(1,0,1), there is a moment that both and are 0, so static 1-hazard happenes.

• Ex1(Removal of static 1-hazard)
  • We can avoid static 1-hazard by adding redudant terms.
  • This method is only workable when there is only one different bit between inputs.

• Ex2(Static 0-hazard)

  • When input chages from (A,B,C,D)=(0,1,0,0) to (A,B,C,D)=(0,1,1,0 ), there is a moment that both and are 1, so static 0-hazard happenes.

• Ex2(Removal of static 0-hazard)

Simulation and Testing of Logic Circuits

To simulate a logic circuit, we need to...

• Specify the circuit components and connections.
• Determine the circuit inputs.
• Observe the circuit outputs.

4-Valued Logic Simulator

• States

  • (low)
  • (high)
  • (Unknown)
    • The value cannot be confirmed.
  • (High Impedance)
    • The input does not receive any value.(空接)

• AND/OR with 4-Valued Simulation

  • AND

  

  • OR

  

• Examples

Verification vs Testing

• When a logic circuit gets a wrong output, it may be due to...
• Verification(Still designing)
  1. Incorrect design
  2. Gates connected wrong
  3. Wrong input signals to the circuit
• Testing(The design of chip is done)
  1. Defective gates
  2. Defective connecting wires